Magnetic Random Access Memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance. MRAM differs from volatile Random Access Memory (RAM) in several respects. Because MRAM is non-volatile, MRAM can maintain memory content when the memory device is not powered. Though non-volatile RAM is typically slower than volatile RAM, MRAM has read and write response times that are comparable to that of volatile RAM. Unlike typical RAM technologies that store data as electric charges, MRAM data is stored by magnetoresistive elements. Generally, the magnetoresistive elements are made from two magnetic layers, each of which holds a magnetization. The magnetization of one layer (the “pinned layer”) is fixed in its magnetic orientation, and the magnetization of the other layer (the “free layer”) can be changed by an external magnetic field generated by a programming current. Thus, the magnetic field of the programming current can cause the magnetic orientations of the two magnetic layers to be either parallel, giving a lower electrical resistance across the layers (“0” state), or antiparallel, giving a higher electrical resistance across the layers (“1” state). The switching of the magnetic orientation of the free layer and the resulting high or low resistance states across the magnetic layers provide for the write and read operations of the typical MRAM cell.
Though MRAM technology offers non-volatility and faster response times, the MRAM cell is limited in scalability and susceptible to write disturbances. The programming current employed to switch between higher and lower electrical resistance states across the MRAM magnetic layers is typically high. Thus, when multiple cells are arranged in an MRAM array, the programming current directed to one memory cell may induce a field change in the free layer of an adjacent cell. This potential for write disturbances, also known as the “half-select problem,” can be addressed using a spin torque transfer technique.
A conventional spin torque transfer MRAM (STT-MRAM) cell may include a magnetic cell stack, which may be a magnetic tunnel junction (MTJ) or a spin valve structure. An MTJ is a magnetoresistive data storing element including two magnetic layers (one pinned and one free) and an insulating layer in between the two magnetic layers; a bit line, a word line; a source line; and an access transistor. A spin valve structure has a structure similar to the MTJ, except a spin valve structure has a conductive layer in between the two magnetic layers. A programming current typically flows through the access transistor and the magnetic cell stack. The pinned layer polarizes the electron spin of the programming current, and torque is created as the spin-polarized current passes through the stack. The spin-polarized electron current interacts with the free layer by exerting a torque on the free layer. When the torque of the spin-polarized electron current passing through the stack is greater than the critical switching current density (JO, the torque exerted by the spin-polarized electron current is sufficient to switch the magnetization of the free layer. Thus, the magnetization of the free layer can be aligned to be either parallel or antiparallel to the pinned layer, and the resistance state across the stack is changed.
The STT-MRAM has advantageous characteristics over the MRAM, because the spin-polarized electron current eliminates the need for an external magnetic field to switch the free layer in the magnetoresistive elements. Further, scalability is improved as the programming current decreases with decreasing cell sizes, and the writing disturbance and half-select problem is addressed. Additionally, STT-MRAM technology allows for a higher tunnel magnetic resistance ratio, meaning there is a larger ratio between higher and lower electrical resistance states, thereby improving read operations in the magnetic domain.
Presently-known STT-MRAM structures and methods for fabricating such structures all suffer from several drawbacks. Structure of a standard 1T-1R STT-MRAM bit-cell could not achieve high density memory for stand-alone market; as such multi-bit per cells is preferred. For example, in some known structures, it has proven difficult to achieve compact design layouts, such as two bit per cell layouts, to afford higher density memory availability while maintaining a small footprint on the semiconductor device. These compact designs have heretofore required the use of complicated three-dimensional structures and a relatively high-operating current, which both adds to fabrication process complexity and power consumption.
Accordingly, with the increasing use of STT-MRAM in stand-alone memory application, it is desirable to provide robust and reliable STT-MRAM structures. Additionally, it is desirable to provide methods for the fabrication of such structures that are easily integrated into existing process flow schemes used in semiconductor fabrication facilities. Still further, it is desirable to provide such structures and methods that allow for the relatively compact two bit per cell architecture without the need for three-dimensional layouts or excessive power consumption. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.